key features ultra-fast response for fast-20 scsi applications 35mhz channel bandwidth 3.3v operation less than 3pf output capacitance sleep-mode current less than 275a thermally self limiting no external compensation capacitors implements 8-bit or 16-bit (wide) applications compatible with active negation drivers (60ma/channel) compatible with passive and active terminations approved for use with scsi 1, 2, 3 and ultrascsi hot swap compatible pin-for-pin compatible with lx5211 and uc5606 (imp5111) pin-for-pin compatible with lx5212 and uc5603/5613/5614 (imp5112) block diagrams + current biasing circuit thermal limiting circuit 24ma current limiting circuit term power data output pin db (0) 1 of 9 channels disconnect (imp5111) disconnect (imp5112) 1.4v 2.85v 5111/5112_01.eps 9-line scsi t 9-line scsi t er er minat minat or or C 35mhz channel bandwidt C 35mhz channel bandwidt h h the 9-channel imp5111/5112 scsi terminator is part of imp's family of high-performance scsi terminators that deliver true ultrascsi per- formance. the bicmos design offers superior performance over first generation linear regulator/resistor based terminators. imp's new architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible - typically 35mhz, which is 100 times faster than the older linear regulator termi- nator approach. the bandwidth of terminators based on the older regulator/resistor terminator architecture is limited to 500khz since a large output stabilization capacitor is required. the imp architecture eliminates the external output compensation capacitor and the need for transient output capacitors while maintaining pin compatibility with first generation designs. reduced component count is inherent with the imp5111/5112. the imp5111/5112 architecture tolerates marginal system designs. a key improvement offered by the imp5111/5112 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended scsi hardware design guidelines, such as improper cable lengths and impedance. frequently, this situation is not controlled by the peripheral or host designer. for portable and configurable peripherals, the imp5111/5112 can be placed in a sleep mode with a disconnect signal. quiescent current is less than 275 a when disabled. when disabled, the outputs are in a high impedance state with output capacitance less than 3pf. ? 200 2 im p , inc. 408-432-9100/ww w .impweb.com 1 imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2 d ata c ommunications ? 200 2 im p , inc. 408-432-9100/ww w .impweb.com 1 imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2 d ata c ommunications
2 408-432-9100/ww w .impweb.com ? 200 2 im p , inc. pin configuration ordering information absolute maximum ratings 1 8t2 1t7 dw package 9t3 7t1 10 t4 6disconnect* 11 v term 5gnd 12 heat sink/gnd 4heat sink/gnd 13 heat sink/gnd 3t9 14 nc 2t8 15 t5 16 t6 5111/5112__02.eps imp5111 imp5112 * disconnect (imp5111) disconnect (imp5112) so-16 * disconnect (imp5111) disconnect (imp5112) 12t2 1t7 pw package 13 t3 7heat sink/gnd 18 heat sink/gnd 8heat sink/gnd 17 heat sink/gnd 9heat sink/gnd 16 nc 10disconnect* 15 v term 11t1 14 t4 6heat sink/gnd 19 heat sink/gnd 5gnd 20 heat sink/gnd 4nc 21 nc 3t9 22 nc 2t8 23 t5 24 t6 5111/5112_02a.eps imp5111 imp5112 tssop-24 rebmuntra pe gnarerutarepme te gakcap pdc1115pm i0 521otc co scitsalpnip-61 tpdc1115pm i0 521otc co scitsalpnip-61,leerdnaepat pwpc1115pm i0 521otc cp osstcitsalpnip-42 tpwpc1115pm i0 521otc cp osstcitsalpnip-42,leerdnaepat pdc2115pm i0 521otc co scitsalpnip-61 tpdc2115pm i0 521otc co scitsalpnip-61,leerdnaepat pwpc2115pm i0 521otc cp osstcitsalpnip-42 tpwpc2115pm i0 521otc cp osstcitsalpnip-42,leerdnaepat 3ta.10t_2115/1115 thermal data termpwr voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +7v signal line voltage . . . . . . . . . . . . . . . . . . . . . . . . 0v to +7v regulator output current . . . . . . . . . . . . . . . . . . 0.4a operating junction temperature plastic (dp, pwp packages) . . . . . . . . . . . . . . . 150 c note: 1. exceeding these ratings could cause damage to the device. all voltages are with respect to ground. currents are positive into, negative out of the specified terminal. storage temperature range . . . . . . . . . . . . . . . . . -65 c to 150 c lead temperature (soldering, 10 seconds) . . . . . 300 c dp package: thermal resistance junction-to-leads, jl . . . . . . . . 2 0 c/w thermal resistance junction-to-ambient, ja . . . . . . 5 0 c/w pw package: thermal resistance junction-to-leads, jl . . . . . . . . 2 7 c/w thermal resistance junction-to-ambient, ja . . . . . . 100 c/w junction temperature calculation: t j = t a + (p d x ja ). the ja numbers are guidelines for the thermal performance of the device/pc-board system. all of the ambient airflow is assumed. imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2 imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2
? 200 2 im p , inc. data communications 3 recommended operating conditions 2 retemara pl obmy sn i mp y tx a ms tinu egatlovrwpmre tv mret 3. 35 . 5v egatlovtupnielbanelevelhgi h1 115pm iv hi 2v mret v 2115pm i08 .0 egatlovtupnielbasidlevelwo l1 115pm iv li 08 . 0v 2115pm i2v mret egnarerutarepmetnoitcnujgnitarepo 05 2 1c .lanoitcnufsiecivedehthcihwrevoegnarehtetacidnisnoitidnocgnitarepodednemmocer.2:eton spe.20t_2115/1115 electrical characteristics unless otherwise specified, these specifications apply at an ambient operating temperature of t a = 25 c. termpwr = 4.75v. low duty cycle pulse testing techniques are used which maintain junction and case temperatures equal to the ambient temperature. retemara pl obmy ss noitidno cn i mp y tx a ms tinu egatlovhgihtuptu ov tuo 56. 25 8. 2v tnerrucylppusrwpmre ti cc nepo=senilatadll a69a m v5.0=senilatadll a5 1 25 22 1115pm it cennocsi dv 8.0ni p5 72 tnerructuptu oi tuo v tuo v5.0 =1 2 32 42 am tcennocsi dt nerructupn i1 115pm ii ni tcennocsi dv 57.4=ni p0 1a n tcennocsi dv 0=ni p0 9 a tcennocsi dt nerructupn i2 115pm ii ni tcennocsi dv 0=ni p0 9 a tcennocsi dv 57.4=ni p0 1a n tnerrucegakaeltuptu o1 115pm ii lo tcennocsi dv ,v8.0nip o v5.0 =0 1 niecnaticapa ct cennocsi de do mc tuo v tuo zhm1=ycneuqerf,v0 =3f p htdiwdnablennah cw b5 3z hm lennahcrep,tnerrucknisnoitanimre ti knis v tuo v4 =0 6a m spe.30t_2115/1115 imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2 imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2
4 408-432-9100/ww w .impweb.com ? 200 2 im p , inc. application information imp5111/imp5112 maximizes line current cable transmission theory suggests to optimize signal speed and quality, the termination should act both as an ideal voltage refer- ence when the line is released (deasserted) and as an ideal current source when the line is active (asserted). common active terminators which consist of linear regulators in series with resis- tors (typically 110 ? ) are a compromise. with coventional linear terminators as the line voltage increases the amount of current decreases linearly by the equation; the imp5111/5112, with their unique architecture, applies the maximum amount of current regardless of line voltage until the termination high threshold (2.85v) is reached. disable /sleep mode the imp5111 has an active low disconnect pin, and the imp5112 has an active high disconnect pin. the disable mode is entered if the disconnect pin on either device is left open. when disabled the termination lines are in a high impedance state, and the power supply current drops to 275 a t ypically. the disable mode can be used to save power or completely eliminate the terminator from the scsi bus. disabled terminators appear as distributed capacitance on the bus. the imp5111/5112 have been optimized to have only 3pf of capacitance per output when in the disabled mode. the imp5111/5112 are compatible with active negation drivers. the devices will handle up to 60ma of sink current for drivers which exceed the 2.85v output high level . vv r i ref line ? () = . figure 3. 5111/5112_03.eps 1 meter, awg 28 imp5111 imp5112 receiver driver imp5111 imp5112 figure 1. receiving waveform ?20mhz figure 2. driving waveform ?20mhz 1115pmi tcennocsid 2115pmi tcennocsid stuptu ot nerructnecseiuq hl d elban ea m6 lh e cnadepmihgih/delbasi d5 72 a nep on ep oe cnadepmihgih/delbasi d5 72 a spe.a40t_2115/1115 table 1. power up/ power down function table imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2 imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2
? 200 2 im p , inc. data communications 5 sehcn is retemillim ni mx a mn i mx am *)nip-61(os a3 50. 09 60. 05 3. 15 7.1 1 a4 00. 00 10. 00 1. 05 2.0 b4 10. 08 10. 05 3. 06 4.0 c7 00. 00 10. 09 1. 05 2.0 d5 83. 04 93. 08 7. 91 0.01 e0 51. 08 51. 01 8. 31 0.4 ec sb050. 0c sb72.1 h8 22. 04 42. 09 7. 50 2.6 l6 10. 00 50. 00 4. 07 2.1 m 0 8 0 8 )nip-42(posst a2 30. 01 40. 00 8. 05 0.1 b7 00. 02 10. 09 1. 00 3.0 c5 300. 01 700. 09 0. 00 81.0 d3 03. 01 13. 00 7. 70 9.7 e9 61. 06 71. 00 3. 48 4.4 fc sb520. 0c sb56.0 g2 00. 05 00. 05 0. 05 1.0 h 3340.0 01.1 l0 20. 08 20. 00 5. 00 7.0 m 0 8 0 8 p6 42. 06 52. 05 2. 60 5.6 ca210-smgniwardcedej* 3ta.60t_2115/1115 h e eb d a1 a l m c 16-pin (so).eps so (16-pin) 321 ep d seating plane b g a h f e l 24-pin (tssop).eps c m tssop (24-pin) package dimensions imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2 imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2
? 200 2 im p , inc. printed in usa publication #: 7007 revision: c issue date: 08 / 19 / 0 2 type: product imp, inc. corporate headquarters 2830 n. first street san jose, ca 95134-2071 tel: 408-432-9100 fax: 408-43 2 - 10 85 e-mail: info@impinc.com http://www.impweb.com the imp logo is a registered trademark of imp, inc. all other company and product names are trademarks of their respective owners. imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2 imp5 imp5 1 1 1 1 1/5 1/5 1 1 1 1 2 2
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